Power MOS devices, including laterally diffused metal-oxide-semiconductor (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. In applications where high-frequency operation is desired, such as in a radio frequency (RF) range (e.g., above 1 gigahertz (GHz)), a conventional LDMOS device may employ a dummy gate structure stacked on the traditional gate to reduce the Miller capacitance Cgd between the gate and drain of the device, thereby improving the high-frequency performance of the device, and to reduce hot-carrier induced (HCI) degradation in the device.
It is known that the effectiveness of the dummy gate, which may be measured by, for example, a reduction in miller capacitance and/or HCI degradation associated with the LDMOS device, can be improved by reducing the thickness of the dielectric layer (gate dielectric) underneath the dummy gate. However, reducing the gate dielectric thickness increases the gate-to-source capacitance Cgs (i.e., input capacitance) of the device, thereby undesirably affecting the high-frequency performance. The increase in the input capacitance of the device resulting from the reduction in gate dielectric thickness often significantly undermines any beneficial reduction in the miller capacitance provided by the dummy gate. Moreover, the conventional dummy gate structure is generally not compatible with a complementary MOS (CMOS) process technology due, at least in part, to the height of the gate/dummy gate stack. As an added drawback, the conventional dummy gate structure prevents full gate metalization, which is one known method for dramatically reducing the resistance Rg of the gate, thus further limiting the high-frequency performance of the LDMOS device. Since the output gain of the MOS device is inversely proportional to the gate resistance of the device, increasing the gate resistance results in a decrease in the output gain of the device, which is particularly undesirable in an amplifier application.
Previous attempts to improve the high-frequency performance of the LDMOS device have primarily focused on optimizing the trade-off between dummy gate effectiveness and input capacitance. These prior attempts, however, have been unsuccessful at providing a CMOS process compatible LDMOS device capable of high-frequency operation. Accordingly, there exists a need for an LDMOS device capable of improved high-frequency performance without increasing HCI degradation in the device. Furthermore, it would be desirable if such an LDMOS device was fully compatible with a CMOS process technology.